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<title>VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values </title></head>
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<h1>VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.128.F3.0F.W0 7A /r</p>
<p>VCVTUDQ2PD xmm1 {k1}{z}, xmm2/m64/m32bcst</p></td>
<td>HV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Convert two packed unsigned doubleword integers from ymm2/m64/m32bcst to packed double-precision floating-point values in zmm1 with writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.F3.0F.W0 7A /r</p>
<p>VCVTUDQ2PD ymm1 {k1}{z}, xmm2/m128/m32bcst</p></td>
<td>HV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Convert four packed unsigned doubleword integers from xmm2/m128/m32bcst to packed double-precision floating-point values in zmm1 with writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.F3.0F.W0 7A /r</p>
<p>VCVTUDQ2PD zmm1 {k1}{z}, ymm2/m256/m32bcst</p></td>
<td>HV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Convert eight packed unsigned doubleword integers from ymm2/m256/m32bcst to eight packed double-precision floating-point values in zmm1 with writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>HV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Converts packed unsigned doubleword integers in the source operand (second operand) to packed double-preci-sion floating-point values in the destination operand (first operand).</p>
<p>The source operand is a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
<p>Attempt to encode this instruction with EVEX embedded rounding is ignored.</p>
<p>Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
<p><strong>Operation</strong></p>
<p><strong>VCVTUDQ2PD (EVEX encoded versions) when src operand is a register</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>k (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197)</p>
<p>Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VCVTUDQ2PD (EVEX encoded versions) when src operand is a memory source</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>k (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN</p>
<p>DEST[i+63:i] (cid:197)</p>
<p>Convert_UInteger_To_Double_Precision_Floating_Point(SRC[31:0])</p>
<p>ELSE</p>
<p>DEST[i+63:i] (cid:197)</p>
<p>Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VCVTUDQ2PD __m512d _mm512_cvtepu32_pd( __m256i a);</p>
<p>VCVTUDQ2PD __m512d _mm512_mask_cvtepu32_pd( __m512d s, __mmask8 k, __m256i a);</p>
<p>VCVTUDQ2PD __m512d _mm512_maskz_cvtepu32_pd( __mmask8 k, __m256i a);</p>
<p>VCVTUDQ2PD __m256d _mm256_cvtepu32_pd( __m128i a);</p>
<p>VCVTUDQ2PD __m256d _mm256_mask_cvtepu32_pd( __m256d s, __mmask8 k, __m128i a);</p>
<p>VCVTUDQ2PD __m256d _mm256_maskz_cvtepu32_pd( __mmask8 k, __m128i a);</p>
<p>VCVTUDQ2PD __m128d _mm_cvtepu32_pd( __m128i a);</p>
<p>VCVTUDQ2PD __m128d _mm_mask_cvtepu32_pd( __m128d s, __mmask8 k, __m128i a);</p>
<p>VCVTUDQ2PD __m128d _mm_maskz_cvtepu32_pd( __mmask8 k, __m128i a);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<table>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E5.</td></tr>
<tr>
<td>If EVEX.vvvv != 1111B.</td></tr></table></body></html>